In a known manner, class-D amplifier circuits are amplification circuits that operate by switching, usually having high efficiency and therefore being recommended for power applications.
FIG. 1 shows a typical configuration of a class-D amplifier circuit, indicated as a whole using reference sign 1, in this case in a differential configuration and including a first and second circuit branch 1a, 1b. 
The first and second circuit branches 1a, 1b receive, respectively, a first input signal VINP (for example positive) and a second input signal VINN (for example negative) at first and second input terminals INP, INN, and output a first output signal (for example negative) VOUTN and a second output signal (for example positive) VOUTP at first and second output terminals OUTN, OUTP.
Each circuit branch 1a, 1b has an output switching circuit 2 comprising an inverter 4, in turn formed by a first MOS transistor 4a, in particular a pMOS transistor, connected between a power input INHV receiving a high power supply voltage VHV and a respective output terminal OUTN or OUTP, and a second MOS transistor 4b, in particular an nMOS transistor, connected between the respective output terminal OUTN or OUTP and a reference terminal (ground, gnd).
Each circuit branch 1a, 1b also includes a comparator circuit 5 that has an output linked to the common gate terminal of the transistors 4a, 4b and is designed to control switching of the output switching circuit 2 between the high power supply voltage VHV and ground. The comparator circuit 5 further includes a first comparison input (for example negative in branch 1a and positive in branch 1b), receiving a triangular-wave voltage, hereinafter simply referred to as triangular voltage, VTRI, from a triangular-voltage generator 6. The comparator circuit 5 also includes a second comparison input (for example positive in branch 1a and negative in branch 1b).
Each circuit branch 1a, 1b also includes a feedback circuit 8, in integrator configuration, comprising an operational transconductance amplifier (OTA) 9, having a first input connected to a respective input terminal INN or INP via an input resistor R1, a second input connected to a reference terminal, and an output connected to the second comparison input of the comparator circuit 5. In particular, an integration resistor R2 is connected such as to form a closed feedback loop between the respective output terminal OUTP or OUTN and the first input of the operational transconductance amplifier 9, and an integration capacitor C1 is connected between said first input and the output of the operational transconductance amplifier 9 (which is also the second comparison input of the comparator circuit 5).
In a known manner not described in detail here, the comparator circuit 5, on the basis of the triangular voltage VTRI, determines a pulse width modulation (PWM), modifying the duty cycle of the output signal VOUTN, VOUTP by varying the amplitude of the respective input signal VINP, VINN, thereby achieving operation with low power dissipation.
In a known manner and as described for example in M. Berkhout, “An integrated 200 W class-D audio amplifier”, IEEE JSSC, July 2003 (incorporated by reference), in order to optimize the performance of the amplifier circuit 1, for example in terms of Power Supply Rejection Ratio (PSRR) and Total Harmonic Distortion (THD), the loop gain needs to be as high as possible, with the restriction that the Gain BandWidth Product (GBWP) be below the stability limit fs/π, where fs is the repetition frequency of the triangular voltage VTRI, which is equal to the inverse of the repetition period Ts.
This requirement is illustrated in FIG. 2, which shows the evolution of the loop gain G as a function of frequency, as well as showing the gain bandwidth product GBWP.
In particular, the gain bandwidth product GBWP is defined by the expression:
            G      ⁢                          ⁢      B      ⁢                          ⁢      W      ⁢                          ⁢      P        =                  1                  2          ⁢          π          ⁢                                          ⁢                      R            2                    ⁢                      C            1                              ⁢                        V          HV                          V          TRI                      ,in which VHV and VTRI represent respectively the amplitude of the high power supply voltage of the output switching circuit 2 and the amplitude of the triangular voltage generated by the triangular-voltage generator 6, and R2 and C1 indicate, as discussed previously, the resistance and capacity of the resistor and the integration capacitor.
The process spread and temperature spread make it difficult to dimension the aforementioned gain bandwidth product GBWP such that the same is actually close to the stability limit fs/π. In particular, a certain margin needs to be left during the design stage for said stability limit, for example 40%, to prevent said limit from being exceeded during operation.
Consequently, the actual gain bandwidth product GBWP during use may deviate substantially from the ideal limit value, with obvious repercussions in terms of the performance levels achievable by the amplifier circuit 1.
A solution that has been proposed to overcome this drawback, given the dependence of said expression of the gain bandwidth product GBWP on the amplitude of the triangular voltage VTRI, involves designing the triangular-voltage generator 6 such that the amplitude VTRI is proportional to the amplitude of the high power supply voltage VHV and inversely proportional to the product R2C1.
Consequently, as shown in the aforementioned expression of the gain bandwidth product GBWP, the dependence of said gain bandwidth product GBWP on the temperature and process spread can be eliminated, or in any case significantly reduced, enabling said gain bandwidth product GBWP to be set very close to the stability limit fs/π.
Furthermore, it is desirable for the mean value of the triangular voltage VTRI to be constant if the comparator circuit 5 of the amplifier circuit 1 is powered by a dedicated power supply voltage VDD, or directly proportional to the amplitude of the high power supply voltage VHV if said comparator circuit 5 is powered by the high power supply voltage VHV.
A known circuit solution for providing a triangular-voltage generator 6 that satisfies the aforementioned requirements is shown in FIG. 3.
In particular, the triangular-voltage generator, again indicated using reference sign 6, includes in this case an operational amplifier 10, in voltage follower configuration, that receives via a non-inverting input terminal a input voltage of KVHV, i.e. equal to K times the amplitude of the high power supply voltage VHV (where K is less than 1), and has an inverting terminal connected to a reference terminal (ground, gnd) via a coupling resistor Rm, and an output terminal connected to the gate terminal of an nMOS transistor 11.
Said nMOS transistor 11 also has a source terminal connected to the inverting terminal of said operational amplifier 10 and a drain terminal connected to a first pMOS current mirror 12 comprising three pMOS transistors 12a, 12b, 12c. 
The current I mirrored by the first current mirror 12 onto a respective output branch is:I=(K/Rm)·VHV,where Rm is the resistance of said coupling resistor.
The triangular-voltage generator 6 also includes a second nMOS current mirror 14 comprising two nMOS transistors 14a, 14b and having a respective output branch that mirrors said current I.
In particular, the output branches of the first and second current mirrors 12 are connected to an internal node N1 via first and second switches 15a, 15b respectively.
The first and second switches 15a, 15b are alternately commanded to open/close in first and second semi-periods Ts/2 of the repetition period Ts, such that in a first half-period Ts/2 the current I is supplied to the internal node N1 from the output branch of the first current mirror 12 (the first switch 15a is closed and the second switch 15b is open), and in a second half-period Ts/2 said current I is taken from said internal node N1 from the output branch of the second current mirror 14 (the first switch 15a is open and the second switch 15b is closed).
The triangular-voltage generator 6 also includes an output integrating circuit formed by an operational amplifier 16, in integrator configuration, having a first terminal (inverting terminal) connected to said internal node N1, a second terminal (non-inverting terminal) that receives a reference voltage VREF, and an output terminal that supplies the triangular voltage VTRI. An integration resistor Ri and an integration capacitor C2 are connected in parallel between the output terminal and the first terminal of the aforementioned operational amplifier 16 (the following equation being true: Ri>>>TS/C2).
It is evident that the amplitude of the triangular voltage VTRI is given by:
            V      TRI        =          k      ⁢                          ⁢              V        HV            ⁢              1                  2          ⁢                      f            S                    ⁢                      R            m                    ⁢                      C            2                                ,and is therefore directly proportional to the amplitude of the high power supply voltage VHV and inversely proportional to the product RmC2.
It is therefore sufficient to ensure that the resistance and capacitance values Rm and C2 are matched to the respective resistance and capacitance values R2 and C1 of the aforementioned product R2C1 in the expression of the gain bandwidth product GBWP of the amplifier circuit 1, such that said amplitude VTRI satisfies the aforementioned requirements, making said gain bandwidth product GBWP substantially independent of the process and temperature spreads.
Furthermore, the mean value VTRI_MEAN of the triangular voltage VTRI (see also FIG. 4) is equal to the value of the reference voltage VREF, which may be constant, if the comparator circuit 5 of the amplifier circuit 1 is powered by the dedicated power supply voltage VDD, or made equal to VHV/2 if said comparator circuit 5 is powered by said high power supply voltage VH.
The inventors further note that the aforementioned triangular-voltage generator 6, although it enables the aforementioned requirements relating to the amplitude of the triangular voltage VTRI to be satisfied, as discussed, it has some drawbacks.
In particular, this implementation includes numerous noise contributors, due for example to the coupling resistor Rm, the operational amplifiers 10, 16 and the MOS transistors of the first and second current mirrors 12, 14.
There are also numerous mismatch and offset factors. Indeed, the offset of the operational amplifier 10 is converted directly into an offset of the mirrored current I, resulting in a corresponding variation in the amplitude of the output voltage. Mismatches in the nMOS and pMOS transistors of the first and second current mirrors 12, 14 create an asymmetry between the leading and trailing edges of the waveform of the output triangular voltage VTRI, thereby creating a variation both in the amplitude and in the mean value of said triangular voltage VTRI. The repetition frequency fs imposes a limit relating to the area of the nMOS and pMOS transistors, for example a high value of said repetition frequency fs results in a reduced area of said nMOS and pMOS transistors, resulting in high offset and noise values. It is also difficult to create an effective balancing network, which needs to provide three different trimming contributions for the adaptation resistor Rm, for the first current mirror 12 and for the second current mirror 14.
This creates a clear need for a triangular generator, in particular for the amplifier circuit 1, that is able to satisfy the requirements relating to the amplitude of the triangular voltage VTRI, without thereby degrading the performance of said amplifier circuit 1, for example in terms of noise and offset.
There is a need in the art to address this requirement.